1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices and, more particularly, to a nonvolatile semiconductor memory device in which data can electrically be written and erased.
2. Description of the Background Art
There are two types of semiconductor memory devices: the one is a volatile memory such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory) and the like, and the other is a nonvolatile memory. Storage data of a volatile memory are all erased when a power supply is OFF. Storage data of a nonvolatile memory are, however, not erased even if the power supply is OFF. As a representative of nonvolatile semiconductor memory devices, there is a PROM (programmable read only memory). The PROM is a semiconductor memory device in which information is written by a user. As one type of the PROM, there is an EEPROM (electrically erasable and programmable ROM) in which written information can electrically be erased so that information can be rewritten any times. An EEPROM in which storage data of all memory cells can be erased in block is called a flash EEPROM.
FIG. 7 is a schematic block diagram showing a fundamental structure of a conventional flash EEPROM. With reference to FIG. 7, the flash EEPROM includes a memory array 1, a row decoder 60, a Y gate 70 and a column decoder 80.
Memory array 1 includes a plurality of memory cells MC arranged in matrix in the directions of rows and columns. Each of memory cells MC is connected to a corresponding bit line 30 and a corresponding word line 50 in memory array 1. A FAMOS (floating-gate avalanche injection MOS) transistor capable of storing charges in a floating gate is employed in each memory cell MC.
FIG. 8 is a cross-sectional view showing structure of a FAMOS transistor. With reference to FIG. 8, the FAMOS transistor includes a control gate 200, a floating gate 210, N type regions 220 and 230 formed on a P type substrate 240, and an insulator layer 250. Floating gate 210 is formed on P type substrate 240 to bridge N type regions 220 and 230, with insulator layer 250 interposed therebetween. Control gate 200 is formed on floating gate 210 with insulator layer 250 interposed therebetween. Control gate 200 and floating gate 210 are both formed of polysilicon. Insulator layer 250 is formed, of an oxide film such as SiO.sub.2 or the like. Oxide film 250 formed between P type substrate 240 and floating gate 210 has such a small thickness as of normally approximately 100 .ANG.. Control gate 200 is connected to a corresponding word line 50 in FIG. 7. The one N type region 220 of the two N type regions is connected as a drain of this MOS transistor to a corresponding bit line 30 in FIG. 7. The other N type region 230 is connected as a source of the MOS transistor to a source line 80 which is common to all memory cells MC in FIG. 7. P type substrate 240 is grounded.
In data writing, high voltage pulses of 12V or less are applied to control gate 200 and drain 220 via word line 50 and bit line 30, respectively. Source 230 is grounded via source line 80. When the high voltage pulses are applied to drain 220, and source 230 is grounded, avalanche breakdown is caused. Free electrons (hot electrons) .crclbar. having high energy and holes .sym. corresponding to these electrons are generated in a depletion layer in the vicinity of drain 220. The holes .sym. flow toward grounded P type substrate 240. Since the high voltage pulses are also applied to control gate 200, the hot electrons .crclbar. are accelerated by an electric field from control gate 200 and then injected into floating gate through thin oxide film 250 formed between floating gate 210 and P type substrate 240.
The electrons injected into floating gate 220 cannot escape therefrom because floating gate 210 is electrically insulated by oxide film 250. Thus, the electrons once injected into floating gate 210 do not leak out from floating gate 210 but stored therein for a long time even after a power supply is cut off. The state where the electrons are stored in floating gate 210 corresponds to data "0", and the state where no electrons are stored in floating gate 210 corresponds to data "1". Therefore, storage data of memory cells MC are held even after the power supply is cut off. If the electrons are stored in floating gate 210, an inversion layer is not easily produced between source 230 and drain 220 (, i.e., a channel region) due to the stored electrons. Thus, if the electrons are stored in floating gate 210, a gate voltage which is required to produce a channel in this MOS transistor (a threshold voltage of this transistor) is raised higher than the gate voltage which is required when no electrons are stored in floating gate 210. That is, no inversion layer is produced in the channel region unless control gate 200 is supplied with a higher voltage than the voltage enabling an inversion layer to be formed in the channel region when no electrons are stored in floating gate 210.
In erasing of the storage data, a high voltage is applied to source 230 via a source line 28, and control gate 200 is grounded via word line 50. This causes a high electric field having a higher potential on source 230 to be applied to a portion between floating gate 210 and source 230. As a result, a tunnel phenomenon occurs in oxide film 250 insulating floating gate 210 and source 230 from each other, so that a current (tunnel current) flows between floating gate 210 and source 230. That is, the electrons leak out from floating gate 210 to source 230 through oxide film 250. Accordingly, the electrons stored in floating gate 210 are removed, so that the threshold voltage of the MOS transistor is lowered. Since source line 28 is commonly connected to respective sources of memory cells MC, as shown in FIG. 7, the storage data of all memory cells MC in memory array 1 are erased in block.
In data reading, control gate 200 and drain 220 are supplied with a supply voltage (normally 5V) and, a voltage relatively close to the supply voltage via corresponding word line 50 and bit line 30, respectively. Source 230 is grounded via source line 28. If no electrons are stored in floating gate 210 (i.e., if storage data is "1"), the threshold voltage of the MOS transistor is low, so that a channel is produced between source 230 and drain 220 in response to the supply voltage applied to control gate 200. If the electrons are stored in floating gate 210 (i.e., if storage data is "0"), however, the threshold voltage of the MOS transistor is high, so that no channel occurs between source 230 and drain 220 even if the supply voltage is applied to control gate 200. Accordingly, the MOS transistor constituting the memory cell, in which the storage data is "1", is turned on in data reading, so that a current flows from corresponding bit line 30 to source line 28. Since the MOS transistor constituting the memory cell, in which the storage data is "0", is in an OFF state even in data reading, no current flows from corresponding bit line 30 to source line 28. Thus, in data reading, a sense amplifier detects whether or not the current flows through a bit line corresponding to the memory cells from which data is to be read. A determination is made as to whether the storage data is "1" or "0", based on a result of this detection.
If a potential to be applied to bit line 30 in data reading is too high, a high electric field is applied to oxide film 250 formed between floating gate 210 and drain 220, and hence the electrons stored in floating gate 210 are drawn to the drain 220 side. Thus, the potential to be applied to bit line 30 is approximately 1-2V. Therefore, a small current flows through the memory cell, in which the storage data is "1" in data reading. Thus, a current sense amplifier is employed to detect this small current.
With reference to FIG. 7 again, address input terminals A0-AK receive an externally applied address signal. This address signal serves to instruct which one of memory cells MC in memory array 1 data is to be read from or written in. An address buffer 100 buffers an applied address signal to apply the buffered address signal to row decoder 60 and column decoder 80.
An input/output buffer 110 is connected to input/output terminals I/O.sub.0 -I/O.sub.N for receiving input data and output data. Input/output buffer 110 applies write data which is externally applied to input/output terminals I/O.sub.0 -I/O.sub.N to a write circuit 90. Further, input/output buffer 110 provides data supplied from a sense amplifier 120 to input/output terminals I/O.sub.0 -I/O.sub.N as read data.
Write circuit 90 supplies a voltage corresponding to the write data applied from input/output buffer 110 to Y gate 70. Sense amplifier 120 detects an output of Y gate 70 and, in response to a result of the detection, supplies a signal voltage corresponding to data "0" or "1" as read data to input/output buffer 110.
Row decoder 60 responds to the address signal from address buffer 100 to select one of word lines 50 in memory array 1. Column decoder 80 responds to the address signal from address buffer 110 to select one of bit lines 30 in memory array 1.
A control circuit 140 controls Y gate 70, column decoder 80, write circuit 90, address buffer 100, input/output buffer 110 and sense amplifier 120 so that they can perform an operation corresponding to each mode.
A terminal T.sub.PP is supplied with an external high voltage V.sub.PP. A terminal T.sub.CC is supplied with an external supply voltage V.sub.CC of a normal level. A switch circuit 600 selectively outputs to predetermined circuitry one of the high voltage V.sub.PP and supply voltage V.sub.CC applied respectively to terminals T.sub.PP and T.sub.CC.
Switch circuit 600 is controlled by control circuit 140 to supply the high voltage V.sub.PP from terminal T.sub.PP to row decoder 60 in data writing. Further, switch circuit 600 is controlled by control circuit 140 to apply the supply voltage V.sub.CC to row decoder 60 in data reading. Switch circuit 600 is further controlled by control circuit 140 to supply the high voltage V.sub.PP to a source line switch 150 in data erasing.
In data writing, Y gate 70 supplies the voltage applied from write circuit 90 to a bit line selected by column decoder 80. Specifically, if write data is "0", Y gate 70 supplies the high voltage V.sub.PP to the selected bit line. If the write data is "1", Y gate 70 holds a potential on the selected bit line at a ground potential. In data writing, row decoder 60 supplies the high voltage V.sub.PP from high voltage switch circuit 600 to a selected word line. In data writing, source line switch 150 applies the ground potential to source line 28. Therefore, if the write data is "0", the electrons generated by avalanche breakdown are injected only into floating gate 210 of a memory transistor (a selected memory transistor) located at the cross-over point between the word line selected by row decoder 60 and the bit line selected by column decoder 80. If the write data is "1", however, no electrons are injected into floating gate 210 since no high voltage is applied to the bit line in the selected memory transistor.
In data reading, row decoder 60 supplies a supply voltage V.sub.CC applied from switch circuit 600, which is lower than the above-described high voltage V.sub.PP, to the selected word line. In data reading, Y gate 70 supplies a low voltage of 1-2V to the bit line selected by column decoder 80. In data reading, source line switch 150 applies a ground potential to source line 28 like the case in data writing. Accordingly, if storage data of the selected memory transistor is "1", a current flows from the selected bit line through drain 220, the channel region and source 230 of the selected memory cell to source line 28. If the storage data of the selected memory transistor is "0", the selected memory transistor is not turned on in response to a gate voltage of approximately 5V, so that no current flows through the selected bit line. Y gate 70 electrically connects only the selected bit line to sense amplifier 120. This enables sense amplifier 120 to detect whether the current flowing through the selected bit line exists or not.
In data erasing, Y gate 70 maintains all bit lines 30 in memory array 1 in a floating state. Row decoder 60 supplies a ground potential to all word lines 50 in memory array 1, in data erasing. Source line switch 150 converts the high voltage V.sub.PP applied from switch circuit 600 into a pulse signal, to apply the pulse signal to source line 28. Therefore, in data erasing, a tunnel phenomenon occurs in each of all memory cells MC in memory array 1, so that the electrons stored in floating gate 210 of the memory transistor, in which the storage data is "0", are removed from floating gate 210. Accordingly, when the data erasing is completed, the storage data of all memory cells MC in memory array 1 are "1".
It is assumed in the following description that the supply potential and the ground potential correspond to a logic high level (or the H level) and a logic low level (or the L level), respectively.
As described in the foregoing, in the EEPROM, data erasing is carried out by forcing the bending of an energy band between floating gate 210 and source 230 so as to make electrons to tunnel from floating gate 210 to source 230, with a high voltage applied between control gate 200 and source 230 of the memory transistor in data erasing. Thus, the amount of electrons drawn out from floating gate 210 varies depending on the magnitude of a high voltage to be applied to source line 28, the time period in which the high voltage is applied (i.e., the pulse width of high voltage pulses), the thickness of oxide film 250 existing between floating gate 210 and source 230, the thickness of oxide film 250 existing between floating gate 210 and control gate 200, and the like.
There are irregularities in manufacture of memory transistors constituting memory array 1. Because of the irregularities, the thickness of oxide film 250, the form of control gate 200 and floating gate 210, the length of the channel region, and the like are not completely uniformed in all memory transistors. It is actually difficult to simultaneously set the storage data of all memory cells MC in memory array 1 to "0" by the above-described collective erasing, due to the irregularities on manufacture of the memory transistors and other various factors such as some causes in actual circuit configurations. More specifically, in some of the memory transistors, in which the storage data is "0", only the stored electrons are completely removed from floating gate 210 in response to a high voltage applied in collective erasing, whereas in the other memory transistors, a larger amount of electrons than those stored in data writing are drawn out from floating gate 210 in response to the high voltage applied in collective erasing. The phenomenon of the latter case, in which the electrons are excessively drawn out from the floating gate, is called an excess erase.
When an excess erase occurs, floating gate 210 is charged to plus, so that an inversion layer is produced between source 230 and drain 220. This means that this memory transistor is in an ON state even if any potential of 0V or more is applied to control gate 200. As a result, in data reading, a current flows through a bit line corresponding to this memory transistor despite the fact that the transistor is in a non-selection state. Thus, if a memory cell connected to the bit line corresponding to the memory transistor subjected to the excess erase is selected, read data is "1" even in case where storage data of the selected memory transistor is "0". In data writing, if data "0" is intended to be written in the excess-erased memory cell or the memory cell connected to the same bit line as that of the excess-erased memory cell, electrons generated by avalanche breakdown in the selected memory cell leak as a channel current of the excess-erased memory cell to the bit line. Thus, electrons are not sufficiently injected into floating gate 210 of the selected memory cell. Accordingly, if the excessively erased memory cell exists, writing characteristics in data writing deteriorate, and further, data writing is disabled. As described above, the excess erase causes the polarity of the threshold value of the memory transistor to be inverted into minus to cause troubles in subsequent data reading and writing.
In order to prevent such an excess erase, the following method is adopted at present. That is, the pulse width of a high voltage pulse (hereinafter referred to as erase pulse) to be applied to source line 28 for data erasing is made smaller. Every time this erase pulse having the shorter pulse width is applied to source line 28 once, the storage data of all the memory, cells in memory array 1 are read, so as to check whether or not all the storage data of memory cells MC in memory array 1 are "1". If there is even one memory cell in which the storage data is not "1", the erase pulse of the shorter pulse width is again applied to source line 28. The confirmation as to whether or not the storage data of the memory cells are "1" after the erase pulse is applied to source line 28, i.e., whether or not the storage data of the memory cells are completely erased, is called erase verifying. Such erase verification and such application of the erase pulse to source line 28 are repeated until the data erasing is completed with respect to all memory cells MC in memory array 1. A flash EEPROM in which excess erase is prevented by such a method is stated in, for example, ISSCC Diqest of Technical Papers (1990), pp. 60-61 and Electronic Information Communication Society Technical Research Papers (May 21, 1990), pp. 73-77.
Incidentally, electrons are already injected into the floating gate of the memory cell transistor before the data erasing. Thus, the floating gate potential of the memory cell transistor is shifted to a negative side in data erasing. Accordingly, referring to FIG. 8, even if a voltage applied to source 230 in data erasing is approximately 12V, a very large electric field is actually induced at oxide film 250 formed between floating gate 210 and source 230. Thus, there is a case that even if a high voltage V.sub.PP for data erasing is applied as a pulse signal with a short pulse width of approximately 10 msec to source 230, electrons are excessively drawn out from floating gate 210 (excess erase). This phenomenon will now be described in more detail in the following.
FIG. 9 is an equivalent circuit diagram of a memory transistor representing a capacitance coupling relationship among a control gate 200, a floating gate 210, a drain 220; a source 230 and a substrate 240. Referring to FIG. 9, reference characters C.sub.CF, C.sub.D, C.sub.C and C.sub.S denote respective capacitances between control gate 200 and floating gate 210, between floating gate 210 and drain 220, between floating gate 210 and substrate 240 and between floating gate 210 and source 230, respectively. Accordingly, nodes N1, N2, N3, N4 and N5 correspond to control gate 200, floating gate 210, source 230, substrate 240 and drain 220; respectively. A potential on floating gate 210 (a potential on node N2) V.sub.FG is expressed by the following equation where Q.sub.FG denotes the amount of charge stored in floating gate 210; V.sub.G, a potential applied to control gate 200; V.sub.D, a potential of drain 220; V.sub.S, a potential of source 230; and V.sub.C, a potential of a channel region between drain 220 and source 230 (a corresponding portion of substrate 240 between drain 220 and source 230). ##EQU1##
In the above equation, C.sub.CF, C.sub.D, C.sub.C and C.sub.S denote respective capacitance values of capacitors C.sub.CF, C.sub.D, C.sub.C and C.sub.S of FIG. 9. C.sub.TOTAL denotes a total of these capacitances; i.e., C.sub.CF +C.sub.D +C.sub.C +C.sub.S. A coupling ratio k.sub.C is defined by the following equation as a ratio of capacitance C.sub.CF between control gate 200 and floating gate 210 to total capacitance C.sub.TOTAL between control gate 200, floating gate 210, drain 220, source 230 and substrate 240. EQU k.sub.C =C.sub.CF /C.sub.TOTAL ( 2)
In addition, a variation .DELTA.V.sub.TH Of a threshold value of this memory transistor viewed from control gate 200, which is caused by storage of electrons in flowing gate 210, is expressed by the following equation. EQU .DELTA.V.sub.TH =-Q.sub.FG /C.sub.CF ( 3)
In data erasing, since control gate 200, drain 220 and substrate 240 are grounded and a high voltage V.sub.PP is applied to source 230, the following relationships V.sub.C =V.sub.C =V.sub.D =0V, V.sub.S =V.sub.PP are satisfied in the above equation (1). Thus, potential V.sub.FC on the floating gate is expressed in the following equation using coupling ratio k.sub.C and threshold variation .DELTA.V.sub.TH according to the above equations (1) to (3). EQU V.sub.FG =C.sub.X V.sub.PP /C.sub.TOTAL -k.sub.C .DELTA.V.sub.TH ( 4)
Accordingly, the potential difference between floating gate 210 and source 230 is expressed by the following equation. EQU (1-C.sub.S /C.sub.TOTAL)V.sub.PP +k.sub.C .DELTA.V.sub.TH ( 5)
The magnitude of the electric field induced between floating gate 210 and source 230 is proportional to the potential difference between floating gate 210 and source 230 and is inversely proportional to the thickness of oxide film 250 formed between floating gate 210 and source 230. Accordingly, if the thickness of the oxide film between floating gate 210 and substrate 240 is 100 .ANG., threshold variation .DELTA.V.sub.TH is 5V, coupling ratio k.sub.C is 0.6, the value of C.sub.S /C.sub.TOTAL is 0.1, and high voltage V.sub.PP is 12V, then the magnitude of the electric field is 13.8 MV/cm. That is, a very strong electric field of 13.8 MV/cm is induced at the oxide film between floating gate 210 and source 230 in data erasing. This strong electric field causes a tunnel phenomenon, so that the electrons are drawn out from floating gate 210.
In general, in order to cause a tunnel phenomenon for drawing the electrons stored in floating gate 210 into source 230, an electric field of 10 MV/cm or more may be induced at oxide film 250 formed between floating gate 210 and source 230. However, at present, an external power source which drives a semiconductor apparatus and provides a highest voltage second to 5V is a power source of 12V.
In a flash EEPROM, since the total amount of current flowing through bit lines in data writing is approximately 1-5 mA, it is difficult to generate a high voltage for data writing within chips. More specifically, when a high voltage is generated within the chips, a high voltage generating circuit such as a charge pump for providing a high voltage by time-sequentially charging a plurality of capacitors is employed. However, such a high voltage generating circuit cannot supply currents of 1-5mA required for data writing. The magnitude I of a current which can be supplied by the charge pump is evaluated by a product of a capacitance value C of a capacitor in use and a charging frequency f of the capacitor. For example, even if capacitance value C is 10 pF and charging frequency f is 10 MHz, supply current I of the charge pump is as small as 100 .mu.A. Thus, a high voltage required for data erasing and data writing must be supplied from an external power source.
For the above reasons, a high voltage of 12V is used in data erasing at present. Consequently, such an excessively strong electric field (13.8 MV/cm) as described above occurs at oxide film 250 between floating gate 210 and source 230 in data erasing, leading to a higher liability for excess erase.
Further, when a gate voltage is 0V in an N channel MOS transistor, an inter-band tunneling phenomenon occurs in an overlapping region of a gate and a drain diffusion region. This phenomenon also occurs in an overlapping region of the gate and a source diffusion region when a source potential is high. The inter-band tunneling occurs when the surface of N type drain and source diffusion regions is in a deep depletion state since the gate voltage is 0V. If the surface of these N type diffusion regions is in the deep depletion state, then an energy band at the boundary between a substrate and an oxide film beneath the gate curves sharply. Thus, electrons of a valence electron band tunnel to a conduction band in the N type diffusion regions. Holes generated at this time flow into the grounded substrate, while the electrons that have tunneled to the conduction band are focused into the N type diffusion regions. A current generated by the flow of the holes into the substrate becomes a leakage current of this N channel MOS transistor. In data erasing, since a high voltage is applied to source 230 of the memory transistor and control gate 200 is thus grounded, such an inter-band tunneling phenomenon occurs.
Referring again to FIG. 9, it is known that the inter-band tunneling phenomenon occurs at a portion 260 in the vicinity of source 230 at an interface between substrate 240 and oxide film 250, in data erasing. Since substrate 240 is grounded, the holes generated by this phenomenon flow as a leakage current to the substrate 240 side, and the electrons that have tunneled to the conduction band flow to the source 230 side together with the electrons drawn out from floating gate 210. The inter-band tunneling phenomenon in the flash EEPROM is described in the article entitled "Subbreakdown Drain Leakage Current in MOSFET", IEEE Electron Device lett., vol. EDL-8, 1987, pp. 515-517 by J. Chen et al., and the article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE", IEEE Tech. Dig. of IEDM 1987, 25. 8, pp. 560-563 by H. Kume et al. According to these documents, a leakage current generated by the inter-band tunneling phenomenon is approximately 10.sup.-8 A for one memory transistor when the potential of source 230 is approximately 10V. Accordingly, in the case of a 1M bit flash EEPROM, if high voltage pulses of 10V are applied to source 230 for data erasing, then a leakage current generated in data erasing is 10 mA. This leakage current causes such various problems as heat generation of chips due to an increase in power consumption, and a decrease in supply voltage. In general, the tolerance of such a leakage current is several 10 mA or less. However, with the capacity of semiconductor apparatus having been increased in recent years, the number of memory transistors of a flash EEPROM has been increased, and the capacity of the flash EEPROM has also been increased up to approximately 16M bit at present. In the case of a 16M bit flash EEPROM, for example, if data erasing is carried out in response to high voltage pulses of 10V, then a leakage current developed in data erasing is 10 mA.times.16, i.e., 160 mA, the value largely exceeding the tolerance. Since a voltage to be applied to source 230 for data erasing is 12V in practice, the actual magnitude of the leakage current is further larger than that value. In such a circumstance, the leakage current generated in data erasing should be reduced as much as possible.
As has been described heretofore, the conventional flash EEPROM repeats the cycle in which the erase pulse having a short pulse width is first applied to the memory array, and then the erase verifying is carried out, in order to prevent an excess erase. Thus, if the memory cell, in which data is not completely erased, is detected by the erase verifying operation, the erase pulse is again applied to all the memory cells in the memory array. Accordingly, the erase pulses applied again to the memory array serve to remove the electrons stored in the floating gate in data writing in the memory transistor, in which data is not yet completely erased. Conversely, the applied erase pulses serve to draw out the electrons originally existing in the floating gate therefrom in the memory transistor, in which data is already completely erased. Consequently, when the data erasing is completed with respect to memory cells in which data is less easily erased, an excess erase occurs in memory cells in which data is easily erased.
Larger the differences in ease of data erasing between the memory cells constituting the memory array are, larger the differences in the number of erase pulses required for a complete erase of data between the memory cells constituting memory array 1 are. There is a case where the erase pulses, which are again applied so as to completely erase the data of the memory cell detected by erase verifying, cannot perform a complete data erase with respect to the memory cell, in which data is less easily erased than the detected memory cell. In this case, the erase pulses are again applied to all the memory cells in the memory array at the time when the memory cell, in which data is less easily erased, is detected by the next erase verifying operation. Therefore, as there are larger differences in ease of data erasing between the memory cells constituting the memory array, the number of the erase pulses applied to the memory array before the data erasing is completed with respect to the memory cell, in which data is least easily erased (i.e., before the data of all the memory cells in the memory array are completely erased) increases. Thus, it is highly possible that an excess erase occurs in many memory cells when the erasing operation is completed.
The differences in ease of data erasing between the memory cells constituting one memory array are due to various factors in the manufacture and the circuit configuration of the device, as described above. Such differences increase with an increase in the number of memory cells constituting one memory array. Therefore, a recent increase in the capacity of semiconductor memory devices, i.e., an increase in the number of bits makes the foregoing disadvantage more significant.